The present invention relates to a semiconductor memory device, and more particularly, to an apparatus for repairing a defect of a semiconductor memory device.
In a semiconductor memory device, defective memory cells can be repaired using X-addresses and Y-addresses. A repairing apparatus using the X-addresses will be described below.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a plurality of banks 100, 110, 120 and 130, each having plural respective cell arrays 102, 112, 122 and 132 and repair information storages 104, 114, 124 and 134.
FIG. 2 is a block diagram of bank 110 illustrated in FIG. 1.
Referring to FIG. 2, bank 110 includes a plurality of cell arrays 112′, 112″, etc., a plurality of repair information storages 114′, 114″, etc., XHIT blocks 111′, 111″, etc., HITB_SUM blocks 119′, etc., a plurality of bit line sense amplifier arrays 113′, 113″, 113′″, etc. and bit line sense amplifier controllers 115′, 115″, 115′″, etc. and a plurality of row control circuits.
Each of the cell arrays 112′, 112″, etc. includes a main word line MWL, a repair main word line RMWL, connected to an MWL driver 116′, 116″, etc. and an RMWL driver 118′, 118″, etc. respectively, which are driven by a block control block 117′, 117″, etc. When a signal BAX<0:M> containing active information and X-address information and a signal BS containing block selection information are applied to the block control block 117′, 117″, etc., the main word line MWL or the repair main word line RMWL are driven according to determination information XHIT and NXE outputted from a repair information storage 114′, 114″, etc.
In other words, the repair information storage stores information about which main word line is defective. When the semiconductor memory device accesses the defective main word line, the repair information storage outputs a signal for allowing the semiconductor memory device to access a repair main word line RMWL, instead of the defective main word line MWL.
FIG. 3 is a block diagram of the repair information storage illustrated in FIGS. 1 and 2.
Referring to FIG. 3, the repair information storage includes a first storage unit 310, a second storage unit 320, and an output unit 330. The first storage unit 310 stores information about whether the repair information storage is used or not, and the second storage unit 320 stores an X-address of a main word line MWL to be repaired. The output unit 330 outputs a signal HITB for driving the repair main word line RMWL when an inputted address ADDRESS<0:N> is identical to the information stored in the second storage unit 320.
The first storage unit 310 and the second storage unit 320 store information about the defects of the semiconductor memory device, and include a plurality of fuses for storing repair information.
The number of repair main word lines RMWL of the cell array is physically identical to the number of repair information storages. That is, when one repair main word line RMWL is provided in each cell array, one repair information storage is provided in each cell array.
In a case where the semiconductor memory device is actually repaired using the repair information storage, if a defective memory cell is found in a specific cell array, a fuse of the first storage unit 310 is cut so as to use the repair information storage. A fuse of the second storage unit 320, which corresponds to an X-address indicating the defective memory cell, is cut. When the fuse of the first storage unit 310 is cut, signals FUSE_PWR and FUSE_EN are activated and transferred to the second storage unit 320. The second storage unit 320 is enabled in response to the signals FUSE_PWR and FUSE_EN. When the inputted address ADDRESS<0:N> is identical to the address stored in the second storage unit 320, that is, when the semiconductor memory device accesses the defective main word line MWL, the second storage unit 320 outputs the signal HIT<0:N> to the output unit 330. The output unit 330 enables the signal HITB to a low level when it receives the active signal ACT and the defect information HIT<0:N>.
The repair information storage of FIG. 3 is, for example, the repair information storage 114″ shown in FIG. 2. Referring again to FIG. 2, the signal HITB 1 is activated to a low level and is inputted to an XHIT block 111″ and an HITB_SUM block 119′. The XHIT block 111″ and the HITB_SUM block 119′ activate the signals XHIT 1 and NXE. In response to the signal NXE, the block control block 117″ does not drive the main word lines MWL. In response to the signal XHIT 1, the block control block 117″ drives the repair main word line RMWL1 of the cell array 112″.
In other words, the repair information storage provided in each cell array stores information about the main word line MWL to be repaired. When the semiconductor memory device accesses the defective main word line MWL, the repair information storage outputs the signal HITB for allowing the semiconductor memory device to access the repair main word line RMWL, instead of the defective main word line MWL.
As described above, the conventional semiconductor memory device includes separate repair information storages for each cell array in order to repair rows. However, the repair information storage occupies the largest area among circuits disposed in the row path, resulting in an increase in total area of the semiconductor memory device.